Categories
FPGA VHDL

Interesting details of ieee.fixed_pkg

Today I learned that in order to assign a negative sfixed (signed fixed-point) signal or variable to another signal or variable, I have to use resize.

process
    variable x0: sfixed(7 downto -8) := to_sfixed(1, 7, -8);
    constant val: sfixed(7 downto -8) := to_sfixed(10, 7, -8);
begin
    -- does not work:
    x0 := -val;
    
    -- this does work:
    x0 := resize(-val, x0);
end process;

So, it seems, internally this is an actual multiplication and not a manipulation on the signed value.

This holds for GHDL 3.0 using the VHDL-2008 standard. No idea yet what other tools do with this.